The disclosed embodiments of the present invention relate to an integrated circuit design, and more particularly, to an integrated circuit having a timing fixing circuit that introduces no short-circuit current under normal operation and an associated timing fixing cell in a cell library.
Setup and hold time checks are the most common types of timing checks used in timing verification of an integrated circuit layout design. For example, synchronous inputs have setup and hold time specification with respect to the clock input. These checks specify that the data input must remain stable for a specified time period just before and just after the clock edge. The time period just before the clock edge is called setup time. The time period just after the clock edge is called hold time. When timing verification of an integrated circuit layout design indicates timing violation (e.g., setup time violation and/or hold time violation), the integrated circuit layout design needs proper modification to meet the timing requirement (e.g., setup time requirement and/or hold time requirement).